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[/] [or1k/] [tags/] [rel_25/] [or1200/] [rtl/] [verilog] - Rev 791

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Rev Log message Author Age Path
791 Fixed some ports in instnatiations that were removed from the modules lampret 8142d 11h /or1k/tags/rel_25/or1200/rtl/verilog
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8142d 11h /or1k/tags/rel_25/or1200/rtl/verilog
788 Some of the warnings fixed. lampret 8142d 12h /or1k/tags/rel_25/or1200/rtl/verilog
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8143d 08h /or1k/tags/rel_25/or1200/rtl/verilog
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8143d 08h /or1k/tags/rel_25/or1200/rtl/verilog
776 Updated defines. lampret 8143d 08h /or1k/tags/rel_25/or1200/rtl/verilog
775 Optimized cache controller FSM. lampret 8143d 08h /or1k/tags/rel_25/or1200/rtl/verilog
774 Removed old files. lampret 8143d 09h /or1k/tags/rel_25/or1200/rtl/verilog
737 Added alternative for critical path in DU. lampret 8158d 03h /or1k/tags/rel_25/or1200/rtl/verilog
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8161d 02h /or1k/tags/rel_25/or1200/rtl/verilog
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8161d 02h /or1k/tags/rel_25/or1200/rtl/verilog
668 Lapsus fixed. simons 8185d 12h /or1k/tags/rel_25/or1200/rtl/verilog
663 No longer using async rst as sync reset for the counter. lampret 8188d 02h /or1k/tags/rel_25/or1200/rtl/verilog
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8188d 23h /or1k/tags/rel_25/or1200/rtl/verilog
636 Fixed combinational loops. lampret 8198d 07h /or1k/tags/rel_25/or1200/rtl/verilog
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8203d 02h /or1k/tags/rel_25/or1200/rtl/verilog
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8207d 19h /or1k/tags/rel_25/or1200/rtl/verilog
597 Fixed OR1200_XILINX_RAM32X1D. lampret 8211d 13h /or1k/tags/rel_25/or1200/rtl/verilog
596 SR[TEE] should be zero after reset. lampret 8211d 18h /or1k/tags/rel_25/or1200/rtl/verilog
595 Fixed 'the NPC single-step fix'. lampret 8212d 13h /or1k/tags/rel_25/or1200/rtl/verilog

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