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[/] [or1k/] [tags/] [rel_25/] [or1200/] [rtl/] [verilog] - Rev 958

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Rev Log message Author Age Path
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 8004d 20h /or1k/tags/rel_25/or1200/rtl/verilog
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 8006d 20h /or1k/tags/rel_25/or1200/rtl/verilog
943 Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers. lampret 8006d 20h /or1k/tags/rel_25/or1200/rtl/verilog
942 Delayed external access at page crossing. lampret 8006d 20h /or1k/tags/rel_25/or1200/rtl/verilog
916 MAC now follows software convention (signed multiply instead of unsigned). lampret 8019d 00h /or1k/tags/rel_25/or1200/rtl/verilog
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8035d 04h /or1k/tags/rel_25/or1200/rtl/verilog
871 Generic flip-flop based memory macro for register file. lampret 8071d 10h /or1k/tags/rel_25/or1200/rtl/verilog
870 Added defines for enabling generic FF based memory macro for register file. lampret 8071d 10h /or1k/tags/rel_25/or1200/rtl/verilog
869 Added generic flip-flop based memory macro instantiation. lampret 8071d 10h /or1k/tags/rel_25/or1200/rtl/verilog
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8142d 09h /or1k/tags/rel_25/or1200/rtl/verilog
794 Added again just recently removed full_case directive lampret 8142d 09h /or1k/tags/rel_25/or1200/rtl/verilog
791 Fixed some ports in instnatiations that were removed from the modules lampret 8142d 10h /or1k/tags/rel_25/or1200/rtl/verilog
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8142d 10h /or1k/tags/rel_25/or1200/rtl/verilog
788 Some of the warnings fixed. lampret 8142d 11h /or1k/tags/rel_25/or1200/rtl/verilog
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8143d 07h /or1k/tags/rel_25/or1200/rtl/verilog
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8143d 07h /or1k/tags/rel_25/or1200/rtl/verilog
776 Updated defines. lampret 8143d 07h /or1k/tags/rel_25/or1200/rtl/verilog
775 Optimized cache controller FSM. lampret 8143d 07h /or1k/tags/rel_25/or1200/rtl/verilog
774 Removed old files. lampret 8143d 07h /or1k/tags/rel_25/or1200/rtl/verilog
737 Added alternative for critical path in DU. lampret 8158d 01h /or1k/tags/rel_25/or1200/rtl/verilog

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