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[/] [or1k/] [tags/] [rel_25/] [or1200/] [rtl/] [verilog] - Rev 994

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994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8025d 15h /or1k/tags/rel_25/or1200/rtl/verilog
993 Fixed IMMU bug. lampret 8025d 15h /or1k/tags/rel_25/or1200/rtl/verilog
984 Disable SB until it is tested lampret 8028d 19h /or1k/tags/rel_25/or1200/rtl/verilog
977 Added store buffer. lampret 8028d 21h /or1k/tags/rel_25/or1200/rtl/verilog
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 8032d 11h /or1k/tags/rel_25/or1200/rtl/verilog
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 8033d 11h /or1k/tags/rel_25/or1200/rtl/verilog
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 8035d 12h /or1k/tags/rel_25/or1200/rtl/verilog
943 Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers. lampret 8035d 12h /or1k/tags/rel_25/or1200/rtl/verilog
942 Delayed external access at page crossing. lampret 8035d 12h /or1k/tags/rel_25/or1200/rtl/verilog
916 MAC now follows software convention (signed multiply instead of unsigned). lampret 8047d 15h /or1k/tags/rel_25/or1200/rtl/verilog
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8063d 19h /or1k/tags/rel_25/or1200/rtl/verilog
871 Generic flip-flop based memory macro for register file. lampret 8100d 01h /or1k/tags/rel_25/or1200/rtl/verilog
870 Added defines for enabling generic FF based memory macro for register file. lampret 8100d 01h /or1k/tags/rel_25/or1200/rtl/verilog
869 Added generic flip-flop based memory macro instantiation. lampret 8100d 01h /or1k/tags/rel_25/or1200/rtl/verilog
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8171d 01h /or1k/tags/rel_25/or1200/rtl/verilog
794 Added again just recently removed full_case directive lampret 8171d 01h /or1k/tags/rel_25/or1200/rtl/verilog
791 Fixed some ports in instnatiations that were removed from the modules lampret 8171d 01h /or1k/tags/rel_25/or1200/rtl/verilog
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8171d 01h /or1k/tags/rel_25/or1200/rtl/verilog
788 Some of the warnings fixed. lampret 8171d 02h /or1k/tags/rel_25/or1200/rtl/verilog
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8171d 22h /or1k/tags/rel_25/or1200/rtl/verilog

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