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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Rev 1139

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1139 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description. lampret 7763d 05h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1132 RFRAM defines comments updated. Altera LPM option added. lampret 7764d 00h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1104 Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. lampret 7883d 17h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1078 Previous check-in was done by mistake. mohor 7924d 11h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1077 Signal scanb_sen renamed to scanb_en. mohor 7924d 11h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 7935d 06h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1055 Removed obsolete comment. lampret 7966d 23h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 7974d 20h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1033 If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. lampret 7975d 07h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 7975d 20h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 7979d 01h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 7979d 03h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7992d 00h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
984 Disable SB until it is tested lampret 7995d 04h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
977 Added store buffer. lampret 7995d 06h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 7998d 20h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 8001d 20h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8030d 04h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
870 Added defines for enabling generic FF based memory macro for register file. lampret 8066d 10h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8137d 10h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v

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