URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_29/] [or1200/] [rtl/] [verilog/] [or1200_except.v] - Rev 610

Rev	Log message	Author	Age	Path
610	Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.	lampret	8264d 01h	/or1k/tags/rel_29/or1200/rtl/verilog/or1200_except.v
595	Fixed 'the NPC single-step fix'.	lampret	8268d 19h	/or1k/tags/rel_29/or1200/rtl/verilog/or1200_except.v
589	No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.	lampret	8269d 01h	/or1k/tags/rel_29/or1200/rtl/verilog/or1200_except.v
571	Changed alignment exception EPCR. Not tested yet.	lampret	8272d 12h	/or1k/tags/rel_29/or1200/rtl/verilog/or1200_except.v
570	Fixed order of syscall and range exceptions.	lampret	8272d 14h	/or1k/tags/rel_29/or1200/rtl/verilog/or1200_except.v
562	Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.	lampret	8273d 03h	/or1k/tags/rel_29/or1200/rtl/verilog/or1200_except.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8284d 01h	/or1k/tags/rel_29/or1200/rtl/verilog/or1200_except.v