OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_7] - Rev 1006

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1006 Import ivang 8015d 01h /or1k/tags/rel_7
1005 Import ivang 8015d 02h /or1k/tags/rel_7
1004 Now every ramdisk image should have init program. simons 8015d 10h /or1k/tags/rel_7
1003 cuc temporary files are deleted upon exiting markom 8015d 10h /or1k/tags/rel_7
1002 Now every ramdisk image should have init program. simons 8015d 10h /or1k/tags/rel_7
1001 fixed load/store state machine verilog generation errors markom 8015d 10h /or1k/tags/rel_7
1000 IC/DC cache enable routines fixed. simons 8015d 11h /or1k/tags/rel_7
999 Now every ramdisk image should have init program. simons 8015d 12h /or1k/tags/rel_7
998 added missing fout initialization markom 8015d 13h /or1k/tags/rel_7
997 PRINTF should be used instead of printf; command redirection repaired markom 8015d 14h /or1k/tags/rel_7
996 some minor bugs fixed markom 8016d 13h /or1k/tags/rel_7
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8016d 21h /or1k/tags/rel_7
993 Fixed IMMU bug. lampret 8016d 21h /or1k/tags/rel_7
992 A bug when cache enabled and bus error comes fixed. simons 8017d 06h /or1k/tags/rel_7
991 Different memory controller. simons 8017d 06h /or1k/tags/rel_7
990 Test is now complete. simons 8017d 06h /or1k/tags/rel_7
989 c++ is making problems so, for now, it is excluded. simons 8018d 14h /or1k/tags/rel_7
988 ORP architecture supported. simons 8019d 05h /or1k/tags/rel_7
987 ORP architecture supported. simons 8019d 13h /or1k/tags/rel_7
986 outputs out of function are not registered anymore markom 8019d 13h /or1k/tags/rel_7

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.