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[/] [or1k/] [tags/] [rel_7] - Rev 807

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Rev Log message Author Age Path
807 sched files moved to support dir markom 8161d 07h /or1k/tags/rel_7
806 uart now partially uses scheduler markom 8161d 07h /or1k/tags/rel_7
805 kbd, fb, vga devices now uses scheduler markom 8161d 08h /or1k/tags/rel_7
804 memory regions can now overlap with MC -- not according to MC spec markom 8162d 01h /or1k/tags/rel_7
803 Free irq handler fixed. simons 8164d 19h /or1k/tags/rel_7
802 Cache and tick timer tests fixed. simons 8166d 06h /or1k/tags/rel_7
801 l.muli instruction added markom 8168d 02h /or1k/tags/rel_7
800 Bug fixed. simons 8168d 23h /or1k/tags/rel_7
799 Wrapping around 512k boundary to simulate real hw. simons 8172d 17h /or1k/tags/rel_7
798 Hardware scroll added. This possible due to the fact that crt is wrapping around 512k boundary. simons 8172d 17h /or1k/tags/rel_7
797 Changed hardcoded address for fake MC to use a define. lampret 8172d 18h /or1k/tags/rel_7
796 Removed unused ports wb_clki and wb_rst_i lampret 8172d 18h /or1k/tags/rel_7
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8172d 22h /or1k/tags/rel_7
794 Added again just recently removed full_case directive lampret 8172d 22h /or1k/tags/rel_7
793 Added synthesis off/on for timescale.v included file. lampret 8172d 22h /or1k/tags/rel_7
792 Fixed port names that changed. lampret 8172d 22h /or1k/tags/rel_7
791 Fixed some ports in instnatiations that were removed from the modules lampret 8172d 22h /or1k/tags/rel_7
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8172d 22h /or1k/tags/rel_7
789 Added response from memory controller (addr 0x60000000) lampret 8172d 23h /or1k/tags/rel_7
788 Some of the warnings fixed. lampret 8172d 23h /or1k/tags/rel_7

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