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[/] [or1k/] [tags/] [stable_0_2_0] - Rev 339

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Rev Log message Author Age Path
339 Added setpc test lampret 8279d 09h /or1k/tags/stable_0_2_0
338 Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) lampret 8279d 09h /or1k/tags/stable_0_2_0
337 Fixed tick timer interrupt reporting by using TTCR[IP] bit. lampret 8279d 09h /or1k/tags/stable_0_2_0
336 VAPI works markom 8280d 04h /or1k/tags/stable_0_2_0
335 some small bugs fixed markom 8280d 05h /or1k/tags/stable_0_2_0
334 removed vapi client file markom 8280d 08h /or1k/tags/stable_0_2_0
333 small bug fixed markom 8280d 11h /or1k/tags/stable_0_2_0
332 removed fixed irq numbering from pic.h; tick timer section added markom 8280d 11h /or1k/tags/stable_0_2_0
331 dependecy is required by history analisis markom 8280d 12h /or1k/tags/stable_0_2_0
330 Cache test lampret 8280d 15h /or1k/tags/stable_0_2_0
329 Now using macros from spr_defs.h lampret 8280d 15h /or1k/tags/stable_0_2_0
328 Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. lampret 8280d 17h /or1k/tags/stable_0_2_0
327 simulate_dc_mmu_load() was calling insn cache/mmu routines instead of data cache/mmu. Fixed. lampret 8280d 17h /or1k/tags/stable_0_2_0
326 More realistic default cache type. lampret 8280d 17h /or1k/tags/stable_0_2_0
325 minor ethernet testbench modifications erez 8281d 20h /or1k/tags/stable_0_2_0
324 added initial ethernet RX simulation (very simple for now) erez 8281d 20h /or1k/tags/stable_0_2_0
323 small fix erez 8281d 20h /or1k/tags/stable_0_2_0
322 IC test repaired.C simons 8282d 00h /or1k/tags/stable_0_2_0
321 added missing gdbcomm files markom 8282d 03h /or1k/tags/stable_0_2_0
320 added prototypes for xxx_vapi_id() erez 8282d 08h /or1k/tags/stable_0_2_0

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