URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0] - Rev 93

Rev	Log message	Author	Age	Path
93	Adding uos.	lampret	8503d 23h	/or1k/tags/stable_0_2_0
92	Tick timer.	lampret	8504d 02h	/or1k/tags/stable_0_2_0
91	Tick timer facility.	lampret	8504d 02h	/or1k/tags/stable_0_2_0
90	Added tick timer.	lampret	8504d 04h	/or1k/tags/stable_0_2_0
89	Minor changes.	lampret	8505d 00h	/or1k/tags/stable_0_2_0
88	Update.	lampret	8505d 11h	/or1k/tags/stable_0_2_0
87	Files required for creation of html files.	lampret	8505d 11h	/or1k/tags/stable_0_2_0
86	Added dh command.	lampret	8505d 11h	/or1k/tags/stable_0_2_0
85	Added dumphex.	lampret	8505d 11h	/or1k/tags/stable_0_2_0
84	Update.	lampret	8505d 11h	/or1k/tags/stable_0_2_0
83	Updates.	lampret	8505d 11h	/or1k/tags/stable_0_2_0
82	Changed pctemp to pcnext.	lampret	8505d 12h	/or1k/tags/stable_0_2_0
80	First import.	lampret	8533d 06h	/or1k/tags/stable_0_2_0
79	Data and instruction cache simulation added.	lampret	8535d 03h	/or1k/tags/stable_0_2_0
78	(i/d)tlb_status	lampret	8658d 17h	/or1k/tags/stable_0_2_0
77	Regular update.	lampret	8658d 17h	/or1k/tags/stable_0_2_0
76	regular update	lampret	8658d 17h	/or1k/tags/stable_0_2_0
75	simgetstr added. eval_mem32 replaced with evalsim_mem32.	lampret	8658d 17h	/or1k/tags/stable_0_2_0
74	Same as DMMU.	lampret	8665d 17h	/or1k/tags/stable_0_2_0
73	Fixed all bugs. Now more or less works. IMMU still has some problems (exception start).	lampret	8665d 17h	/or1k/tags/stable_0_2_0