URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0] - Rev 983

Rev	Log message	Author	Age	Path
983	First checkin	lampret	8029d 06h	/or1k/tags/stable_0_2_0
982	Moved to sim/bin	lampret	8029d 06h	/or1k/tags/stable_0_2_0
981	First checkin.	lampret	8029d 06h	/or1k/tags/stable_0_2_0
980	Removed sim.tcl that shouldn't be here.	lampret	8029d 06h	/or1k/tags/stable_0_2_0
979	Removed old test case binaries.	lampret	8029d 06h	/or1k/tags/stable_0_2_0
978	Added variable delay for SRAM.	lampret	8029d 06h	/or1k/tags/stable_0_2_0
977	Added store buffer.	lampret	8029d 06h	/or1k/tags/stable_0_2_0
976	Added store buffer	lampret	8029d 06h	/or1k/tags/stable_0_2_0
975	First checkin	lampret	8029d 06h	/or1k/tags/stable_0_2_0
974	Enabled what works on or1ksim and disabled other tests.	lampret	8029d 08h	/or1k/tags/stable_0_2_0
973	generated cuc top scheduler builds without syntax errors; not tested yet	markom	8031d 12h	/or1k/tags/stable_0_2_0
972	Interrupt suorces fixed.	simons	8031d 13h	/or1k/tags/stable_0_2_0
971	Now even keyboard test passes.	simons	8031d 16h	/or1k/tags/stable_0_2_0
970	Testbench is now running on ORP architecture platform.	simons	8032d 04h	/or1k/tags/stable_0_2_0
969	Checking in except directory.	lampret	8032d 20h	/or1k/tags/stable_0_2_0
968	Checking in utils directory.	lampret	8032d 20h	/or1k/tags/stable_0_2_0
967	Checking in mul directory.	lampret	8032d 20h	/or1k/tags/stable_0_2_0
966	Checking in cbasic directory.	lampret	8032d 20h	/or1k/tags/stable_0_2_0
965	Checking in basic directory.	lampret	8032d 20h	/or1k/tags/stable_0_2_0
964	Checking in support directory.	lampret	8032d 20h	/or1k/tags/stable_0_2_0