URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0] - Rev 993

Rev	Log message	Author	Age	Path
993	Fixed IMMU bug.	lampret	7997d 02h	/or1k/tags/stable_0_2_0
992	A bug when cache enabled and bus error comes fixed.	simons	7997d 11h	/or1k/tags/stable_0_2_0
991	Different memory controller.	simons	7997d 11h	/or1k/tags/stable_0_2_0
990	Test is now complete.	simons	7997d 11h	/or1k/tags/stable_0_2_0
989	c++ is making problems so, for now, it is excluded.	simons	7998d 19h	/or1k/tags/stable_0_2_0
988	ORP architecture supported.	simons	7999d 10h	/or1k/tags/stable_0_2_0
987	ORP architecture supported.	simons	7999d 18h	/or1k/tags/stable_0_2_0
986	outputs out of function are not registered anymore	markom	7999d 18h	/or1k/tags/stable_0_2_0
985	DTLB translation doesn't work on or1ksim when IC/DC enabled.	lampret	8000d 06h	/or1k/tags/stable_0_2_0
984	Disable SB until it is tested	lampret	8000d 06h	/or1k/tags/stable_0_2_0
983	First checkin	lampret	8000d 08h	/or1k/tags/stable_0_2_0
982	Moved to sim/bin	lampret	8000d 08h	/or1k/tags/stable_0_2_0
981	First checkin.	lampret	8000d 08h	/or1k/tags/stable_0_2_0
980	Removed sim.tcl that shouldn't be here.	lampret	8000d 08h	/or1k/tags/stable_0_2_0
979	Removed old test case binaries.	lampret	8000d 08h	/or1k/tags/stable_0_2_0
978	Added variable delay for SRAM.	lampret	8000d 08h	/or1k/tags/stable_0_2_0
977	Added store buffer.	lampret	8000d 08h	/or1k/tags/stable_0_2_0
976	Added store buffer	lampret	8000d 08h	/or1k/tags/stable_0_2_0
975	First checkin	lampret	8000d 08h	/or1k/tags/stable_0_2_0
974	Enabled what works on or1ksim and disabled other tests.	lampret	8000d 10h	/or1k/tags/stable_0_2_0