OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc1/] [or1ksim/] [cache/] [icache_model.c] - Rev 1358

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7080d 23h /or1k/tags/stable_0_2_0_rc1/or1ksim/cache/icache_model.c
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7090d 02h /or1k/tags/stable_0_2_0_rc1/or1ksim/cache/icache_model.c
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7103d 05h /or1k/tags/stable_0_2_0_rc1/or1ksim/cache/icache_model.c
1308 Gyorgy Jeney: extensive cleanup phoenix 7294d 20h /or1k/tags/stable_0_2_0_rc1/or1ksim/cache/icache_model.c
1085 Bug fixed. simons 7901d 22h /or1k/tags/stable_0_2_0_rc1/or1ksim/cache/icache_model.c
997 PRINTF should be used instead of printf; command redirection repaired markom 7991d 11h /or1k/tags/stable_0_2_0_rc1/or1ksim/cache/icache_model.c
992 A bug when cache enabled and bus error comes fixed. simons 7993d 02h /or1k/tags/stable_0_2_0_rc1/or1ksim/cache/icache_model.c
884 code cleaning - a lot of global variables moved to runtime struct markom 8035d 09h /or1k/tags/stable_0_2_0_rc1/or1ksim/cache/icache_model.c
638 TLBTR CI bit is now working properly. simons 8193d 22h /or1k/tags/stable_0_2_0_rc1/or1ksim/cache/icache_model.c
631 Real cache access is simulated now. simons 8196d 21h /or1k/tags/stable_0_2_0_rc1/or1ksim/cache/icache_model.c
541 lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES! markom 8218d 06h /or1k/tags/stable_0_2_0_rc1/or1ksim/cache/icache_model.c
429 cache configuration added markom 8246d 05h /or1k/tags/stable_0_2_0_rc1/or1ksim/cache/icache_model.c
428 cache configuration added markom 8246d 05h /or1k/tags/stable_0_2_0_rc1/or1ksim/cache/icache_model.c
261 modified memory accesses; added cfg script; added pic test basic entry of vga; some extensions to mc markom 8285d 09h /or1k/tags/stable_0_2_0_rc1/or1ksim/cache/icache_model.c
167 - SPR values corrected
- testbenches now work
- lot of optimizations, use --disable-debugmod for optimal performance
- some tick timer bugs fixed		 markom 8371d 05h /or1k/tags/stable_0_2_0_rc1/or1ksim/cache/icache_model.c
110 bug fix. markom 8449d 08h /or1k/tags/stable_0_2_0_rc1/or1ksim/cache/icache_model.c
102 Major update to include PM, PIC, Cache Mngmnt and non-interactive mode. lampret 8453d 14h /or1k/tags/stable_0_2_0_rc1/or1ksim/cache/icache_model.c
76 regular update lampret 8653d 12h /or1k/tags/stable_0_2_0_rc1/or1ksim/cache/icache_model.c
26 Clean up. lampret 8830d 16h /or1k/tags/stable_0_2_0_rc1/or1ksim/cache/icache_model.c
5 Data and instruction cache simulation added. lampret 8894d 22h /or1k/tags/stable_0_2_0_rc1/or1ksim/cache/icache_model.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.