OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc1/] [or1ksim/] [sim-config.c] - Rev 1369

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1369 Cleanup FB peripheral, useing the new callbacks nogj 7067d 02h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.c
1368 Cleanup VGA peripheral useing the new callbacks nogj 7067d 02h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.c
1367 Cleanup uart peripheral useing the new callback mechanism nogj 7067d 02h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.c
1361 Cleanup test peripheral nogj 7067d 02h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.c
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7067d 02h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.c
1353 Modularise simulator command parsing nogj 7076d 05h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.c
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7076d 05h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.c
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7089d 09h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.c
1308 Gyorgy Jeney: extensive cleanup phoenix 7281d 00h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.c
1205 fix for gdb_debug config phoenix 7515d 08h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.c
1098 small bug in cuc fixed markom 7875d 12h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.c
1076 channels integration rprescott 7912d 02h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.c
998 added missing fout initialization markom 7977d 14h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.c
997 PRINTF should be used instead of printf; command redirection repaired markom 7977d 14h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.c
970 Testbench is now running on ORP architecture platform. simons 7985d 01h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.c
912 Reset SR (and ESR) have TEE set to zero (no tick timer). lampret 8001d 14h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.c
897 improved CUC GUI; pre/unroll bugs fixed markom 8014d 07h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.c
889 Modified Ethernet model. ivang 8019d 05h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.c
883 cuc updated, cuc prompt parsing; CSM analysis markom 8022d 08h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.c
876 Beta release of ATA simulation rherveille 8029d 00h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.c

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.