OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc1/] [or1ksim/] [testbench/] [mmu_asm.S] - Rev 1765

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5623d 05h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/mmu_asm.S
1572 This commit was manufactured by cvs2svn to create tag 'stable_0_2_0_rc1'. 6897d 12h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/mmu_asm.S
639 MMU cache inhibit bit test added. simons 8217d 06h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/mmu_asm.S
600 No more low/high priority interrupts (PICPR removed). Added tick timer exception. simons 8230d 05h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/mmu_asm.S
475 l.jalr r9 is not used any more. simons 8261d 15h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/mmu_asm.S
415 DTLB test tested on simulator. simons 8273d 04h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/mmu_asm.S
413 some section changes markom 8273d 14h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/mmu_asm.S
410 MMU test added. simons 8274d 11h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/mmu_asm.S

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.