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[/] [or1k/] [tags/] [stable_0_2_0_rc1/] [or1ksim] - Rev 640

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Rev Log message Author Age Path
640 Merge profiler and mprofiler with sim. ivang 8190d 17h /or1k/tags/stable_0_2_0_rc1/or1ksim
639 MMU cache inhibit bit test added. simons 8193d 07h /or1k/tags/stable_0_2_0_rc1/or1ksim
638 TLBTR CI bit is now working properly. simons 8193d 08h /or1k/tags/stable_0_2_0_rc1/or1ksim
633 Bug fix in command line parser. ivang 8194d 13h /or1k/tags/stable_0_2_0_rc1/or1ksim
632 profiler and mprofiler merged into sim. ivang 8195d 08h /or1k/tags/stable_0_2_0_rc1/or1ksim
631 Real cache access is simulated now. simons 8196d 07h /or1k/tags/stable_0_2_0_rc1/or1ksim
630 some bug fixes in store buffer analysis markom 8196d 16h /or1k/tags/stable_0_2_0_rc1/or1ksim
629 typo fixed markom 8196d 19h /or1k/tags/stable_0_2_0_rc1/or1ksim
627 or32 restored markom 8196d 20h /or1k/tags/stable_0_2_0_rc1/or1ksim
626 store buffer added markom 8196d 20h /or1k/tags/stable_0_2_0_rc1/or1ksim
624 Added logging of writes/read to/from SPR registers. ivang 8197d 12h /or1k/tags/stable_0_2_0_rc1/or1ksim
623 update based on recent changes; arithmetic instructions does not modify carry yet markom 8197d 14h /or1k/tags/stable_0_2_0_rc1/or1ksim
622 Cache test works on hardware. simons 8197d 17h /or1k/tags/stable_0_2_0_rc1/or1ksim
621 Cache test works on hardware. simons 8197d 18h /or1k/tags/stable_0_2_0_rc1/or1ksim
620 use ARITH_SET_FLAG to turn off set flag by arith. instructions markom 8197d 19h /or1k/tags/stable_0_2_0_rc1/or1ksim
619 all test pass, after newest changes markom 8197d 19h /or1k/tags/stable_0_2_0_rc1/or1ksim
616 flags test added markom 8200d 14h /or1k/tags/stable_0_2_0_rc1/or1ksim
615 cmov and extxx instructions; add, addi, and, andi now set flag markom 8200d 14h /or1k/tags/stable_0_2_0_rc1/or1ksim
612 Tick timer period extended to meet real timing. simons 8201d 19h /or1k/tags/stable_0_2_0_rc1/or1ksim
611 EEAR register is not changed by trap, sys, int, tick and range exception. simons 8202d 21h /or1k/tags/stable_0_2_0_rc1/or1ksim

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