URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [cpu/] [common/] [parse.c] - Rev 36

Rev	Log message	Author	Age	Path
36	Fixed bug when loading "data" from .text segment (all insns are not only decoded but also placed in simulator memory undecoded as data).	lampret	8802d 17h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/common/parse.c
30	Updated SPRs, exceptions. Added 16450 device.	lampret	8806d 19h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/common/parse.c
28	Adding COFF loader.	lampret	8821d 16h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/common/parse.c
26	Clean up.	lampret	8837d 13h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/common/parse.c
22	More modifications related to or16.	lampret	8839d 20h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/common/parse.c
18	or16 added, or1k renamed to or32.	lampret	8840d 09h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/common/parse.c
6	Just a regular update with exception of cache simulation. MMU simulation still under development.	lampret	8901d 20h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/common/parse.c
3	This commit was generated by cvs2svn to compensate for changes in r2, which included commits to RCS files with non-trunk default branches.	cvs	9027d 13h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/common/parse.c
2	First import.	cvs	9027d 13h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/common/parse.c