OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [cpu/] [or1k/] [sprs.c] - Rev 1780

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5596d 00h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/sprs.c
1611 This commit was manufactured by cvs2svn to create tag 'stable_0_2_0_rc2'. 6796d 10h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/sprs.c
1579 Add missing break; statements nogj 6854d 12h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/sprs.c
1557 Fix most warnings issued by gcc4 nogj 6878d 14h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/sprs.c
1551 Remove the pcprev global nogj 6940d 03h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/sprs.c
1550 * prototype() -> prototype(void) where appropriate.
* Use `static' where it can be used.
nogj 6940d 03h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/sprs.c
1549 Spelling fixes nogj 6940d 03h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/sprs.c
1540 * Breakup the tick_job function into smaller ones.
* Fix lots of conner cases.
* Add tests for the tick timer.
nogj 6940d 03h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/sprs.c
1532 Add pretty spr dumping code nogj 6944d 03h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/sprs.c
1531 Remove non-trigerable out-of-range checks nogj 6944d 03h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/sprs.c
1529 * The effective address as written to the I/DCBPR registers needs to be translated by the respective mmu.
* Don't treat any values as special in the handling of DCPBR, DCBFR, DCBIR, ICBPR and ICBIR.
nogj 6945d 05h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/sprs.c
1513 Remove the flag global nogj 6945d 11h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/sprs.c
1508 Remove m{f,t}spr calls where we can access the spr directly nogj 6945d 11h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/sprs.c
1486 * Seporate out the code used for handling the memory peripheral to peripheral/memory.c
* Mostly decouple the memory controller from the internals of the memory handling.
* Rewrite memory handling to be more linear and thus much faster.
* Issue a bus error on read/write with invalid granularity.
nogj 6988d 12h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/sprs.c
1471 Rewrite the interactive mode handling to also work in the recompiler nogj 7036d 07h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/sprs.c
1452 Implement a dynamic recompiler to speed up the execution nogj 7036d 07h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/sprs.c
1446 Cosmetic fixes nogj 7036d 07h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/sprs.c
1432 Collect most of the cpu state variables in a structure (cpu_state) nogj 7036d 07h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/sprs.c
1404 Move the function of ic_clock() to mtspr() and remove it nogj 7036d 07h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/sprs.c
1402 Do what dc_clock() did in mtspr() and remove it nogj 7036d 07h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/sprs.c

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.