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[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [cache/] [dcache_model.c] - Rev 1555

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1555 * Moved log2_int() from cuc/cuc.c as it is usefull for other things aswell.
* Changed code to use log2_int() instead of log2(), which is also a builtin
library function (fixes compile on gcc4).
* Moved is_power2() from sim-config.c to misc.c.		 nogj 6905d 02h /or1k/tags/stable_0_2_0_rc3/or1ksim/cache/dcache_model.c
1506 * Remove very slow {set,test}sprbit{,s} functions.
* Remove uses of getsprbits in time critical functions.		 nogj 6971d 23h /or1k/tags/stable_0_2_0_rc3/or1ksim/cache/dcache_model.c
1486 * Seporate out the code used for handling the memory peripheral to peripheral/memory.c
* Mostly decouple the memory controller from the internals of the memory handling.
* Rewrite memory handling to be more linear and thus much faster.
* Issue a bus error on read/write with invalid granularity.		 nogj 7014d 23h /or1k/tags/stable_0_2_0_rc3/or1ksim/cache/dcache_model.c
1432 Collect most of the cpu state variables in a structure (cpu_state) nogj 7062d 18h /or1k/tags/stable_0_2_0_rc3/or1ksim/cache/dcache_model.c
1402 Do what dc_clock() did in mtspr() and remove it nogj 7062d 19h /or1k/tags/stable_0_2_0_rc3/or1ksim/cache/dcache_model.c
1386 Rework exception handling nogj 7068d 22h /or1k/tags/stable_0_2_0_rc3/or1ksim/cache/dcache_model.c
1382 Nir Mor:
Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.		 nogj 7077d 22h /or1k/tags/stable_0_2_0_rc3/or1ksim/cache/dcache_model.c
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7103d 13h /or1k/tags/stable_0_2_0_rc3/or1ksim/cache/dcache_model.c
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7112d 17h /or1k/tags/stable_0_2_0_rc3/or1ksim/cache/dcache_model.c
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7125d 20h /or1k/tags/stable_0_2_0_rc3/or1ksim/cache/dcache_model.c
1308 Gyorgy Jeney: extensive cleanup phoenix 7317d 11h /or1k/tags/stable_0_2_0_rc3/or1ksim/cache/dcache_model.c
1085 Bug fixed. simons 7924d 13h /or1k/tags/stable_0_2_0_rc3/or1ksim/cache/dcache_model.c
997 PRINTF should be used instead of printf; command redirection repaired markom 8014d 02h /or1k/tags/stable_0_2_0_rc3/or1ksim/cache/dcache_model.c
992 A bug when cache enabled and bus error comes fixed. simons 8015d 17h /or1k/tags/stable_0_2_0_rc3/or1ksim/cache/dcache_model.c
884 code cleaning - a lot of global variables moved to runtime struct markom 8058d 00h /or1k/tags/stable_0_2_0_rc3/or1ksim/cache/dcache_model.c
638 TLBTR CI bit is now working properly. simons 8216d 13h /or1k/tags/stable_0_2_0_rc3/or1ksim/cache/dcache_model.c
631 Real cache access is simulated now. simons 8219d 12h /or1k/tags/stable_0_2_0_rc3/or1ksim/cache/dcache_model.c
541 lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES! markom 8240d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/cache/dcache_model.c
428 cache configuration added markom 8268d 20h /or1k/tags/stable_0_2_0_rc3/or1ksim/cache/dcache_model.c
261 modified memory accesses; added cfg script; added pic test basic entry of vga; some extensions to mc markom 8308d 00h /or1k/tags/stable_0_2_0_rc3/or1ksim/cache/dcache_model.c

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