OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [cpu/] [common] - Rev 35

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
35 SLP hooks. lampret 8827d 19h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/common
34 Started with SLP (not finished yet). lampret 8827d 19h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/common
32 Interrupt recognition. lampret 8831d 18h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/common
30 Updated SPRs, exceptions. Added 16450 device. lampret 8831d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/common
29 Adding OR16/OR32 insn decoder. lampret 8846d 18h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/common
28 Adding COFF loader. lampret 8846d 18h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/common
26 Clean up. lampret 8862d 15h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/common
25 Bug fix in handling labels when loading code into simulator memory. lampret 8862d 15h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/common
24 Static branch prediction added. lampret 8862d 15h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/common
22 More modifications related to or16. lampret 8864d 22h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/common
18 or16 added, or1k renamed to or32. lampret 8865d 11h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/common
13 Rebuild of the generated files. jrydberg 8926d 03h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/common
7 Major update of the enviorment. Now uses autoconf and automake. The
simulator uses readline aswell to get input from the user. A number of
new files added, some modified. The libc directory is now called support.
jrydberg 8926d 04h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/common
6 Just a regular update with exception of cache simulation. MMU simulation still under development. lampret 8926d 22h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/common
3 This commit was generated by cvs2svn to compensate for changes in r2, which
included commits to RCS files with non-trunk default branches.
cvs 9052d 15h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/common

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.