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[/] [or1k/] [tags/] [stable_0_2_0_rc3] - Rev 357

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Rev Log message Author Age Path
357 Fixed dbg_is_o assignment width. lampret 8300d 20h /or1k/tags/stable_0_2_0_rc3
356 Break point bug fixed simons 8300d 22h /or1k/tags/stable_0_2_0_rc3
355 uart VAPI model improved; changes to MC and eth. markom 8301d 06h /or1k/tags/stable_0_2_0_rc3
354 Fixed width of du_except. lampret 8301d 16h /or1k/tags/stable_0_2_0_rc3
353 Cashes disabled. simons 8302d 03h /or1k/tags/stable_0_2_0_rc3
352 OR1200_REGISTERED_OUTPUTS can now be enabled. lampret 8303d 06h /or1k/tags/stable_0_2_0_rc3
351 Fixed some l.trap typos. lampret 8303d 07h /or1k/tags/stable_0_2_0_rc3
350 For GDB changed single stepping and disabled trap exception. lampret 8303d 09h /or1k/tags/stable_0_2_0_rc3
349 Some bugs regarding cache simulation fixed. simons 8304d 21h /or1k/tags/stable_0_2_0_rc3
348 Added instructions on how to build configure. ivang 8306d 05h /or1k/tags/stable_0_2_0_rc3
347 Added CRC32 calculation to Ethernet erez 8307d 02h /or1k/tags/stable_0_2_0_rc3
346 Improved Ethernet simulation erez 8307d 04h /or1k/tags/stable_0_2_0_rc3
345 Added check for net/ethernet.h (needed by ethernet simulator) erez 8307d 04h /or1k/tags/stable_0_2_0_rc3
344 added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model markom 8307d 06h /or1k/tags/stable_0_2_0_rc3
343 Small touches to test programs erez 8307d 08h /or1k/tags/stable_0_2_0_rc3
342 added exception vectors to support and modified section names markom 8308d 05h /or1k/tags/stable_0_2_0_rc3
341 added VAPI for uart; uart 16550 support, some bugs fixed markom 8308d 06h /or1k/tags/stable_0_2_0_rc3
340 Added hpint vector lampret 8308d 07h /or1k/tags/stable_0_2_0_rc3
339 Added setpc test lampret 8308d 07h /or1k/tags/stable_0_2_0_rc3
338 Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) lampret 8308d 07h /or1k/tags/stable_0_2_0_rc3

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