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[/] [or1k/] [tags/] [stable_0_2_0_rc3] - Rev 630

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Rev Log message Author Age Path
630 some bug fixes in store buffer analysis markom 8204d 04h /or1k/tags/stable_0_2_0_rc3
629 typo fixed markom 8204d 07h /or1k/tags/stable_0_2_0_rc3
627 or32 restored markom 8204d 08h /or1k/tags/stable_0_2_0_rc3
626 store buffer added markom 8204d 08h /or1k/tags/stable_0_2_0_rc3
625 Bus error bug fixed. Cache routines added. simons 8205d 00h /or1k/tags/stable_0_2_0_rc3
624 Added logging of writes/read to/from SPR registers. ivang 8205d 01h /or1k/tags/stable_0_2_0_rc3
623 update based on recent changes; arithmetic instructions does not modify carry yet markom 8205d 03h /or1k/tags/stable_0_2_0_rc3
622 Cache test works on hardware. simons 8205d 06h /or1k/tags/stable_0_2_0_rc3
621 Cache test works on hardware. simons 8205d 07h /or1k/tags/stable_0_2_0_rc3
620 use ARITH_SET_FLAG to turn off set flag by arith. instructions markom 8205d 07h /or1k/tags/stable_0_2_0_rc3
619 all test pass, after newest changes markom 8205d 07h /or1k/tags/stable_0_2_0_rc3
618 Fixed display of new 'void' nop insns. lampret 8205d 16h /or1k/tags/stable_0_2_0_rc3
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8205d 16h /or1k/tags/stable_0_2_0_rc3
616 flags test added markom 8208d 02h /or1k/tags/stable_0_2_0_rc3
615 cmov and extxx instructions; add, addi, and, andi now set flag markom 8208d 02h /or1k/tags/stable_0_2_0_rc3
614 Changed to support new debug if. simons 8208d 09h /or1k/tags/stable_0_2_0_rc3
613 init: trap exception occurs always; initialization of sr not needed anymore markom 8209d 06h /or1k/tags/stable_0_2_0_rc3
612 Tick timer period extended to meet real timing. simons 8209d 08h /or1k/tags/stable_0_2_0_rc3
611 EEAR register is not changed by trap, sys, int, tick and range exception. simons 8210d 09h /or1k/tags/stable_0_2_0_rc3
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8210d 09h /or1k/tags/stable_0_2_0_rc3

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