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[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_alu.v] - Rev 1774

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1765 root 5732d 03h /or1k/trunk/or1200/rtl/verilog/or1200_alu.v
1334 l.ff1 and l.cmov instructions added andreje 7255d 16h /or1k/trunk/or1200/rtl/verilog/or1200_alu.v
1293 Non-functional changes. Coding style fixes. lampret 7468d 07h /or1k/trunk/or1200/rtl/verilog/or1200_alu.v
1284 Added some l.cust5 custom instructions as example lampret 7498d 06h /or1k/trunk/or1200/rtl/verilog/or1200_alu.v
1267 Merged branch_qmem into main tree. lampret 7532d 17h /or1k/trunk/or1200/rtl/verilog/or1200_alu.v
1159 No functional changes. Added defines to disable implementation of multiplier/MAC lampret 7880d 01h /or1k/trunk/or1200/rtl/verilog/or1200_alu.v
1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 8107d 20h /or1k/trunk/or1200/rtl/verilog/or1200_alu.v
1033 If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. lampret 8108d 06h /or1k/trunk/or1200/rtl/verilog/or1200_alu.v
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 8108d 20h /or1k/trunk/or1200/rtl/verilog/or1200_alu.v
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 8112d 03h /or1k/trunk/or1200/rtl/verilog/or1200_alu.v
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8270d 09h /or1k/trunk/or1200/rtl/verilog/or1200_alu.v
794 Added again just recently removed full_case directive lampret 8270d 09h /or1k/trunk/or1200/rtl/verilog/or1200_alu.v
788 Some of the warnings fixed. lampret 8270d 10h /or1k/trunk/or1200/rtl/verilog/or1200_alu.v
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8331d 00h /or1k/trunk/or1200/rtl/verilog/or1200_alu.v
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8344d 19h /or1k/trunk/or1200/rtl/verilog/or1200_alu.v
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8355d 17h /or1k/trunk/or1200/rtl/verilog/or1200_alu.v

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