URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_du.v] - Rev 660

Rev	Log message	Author	Age	Path
660	Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.	lampret	8316d 23h	/or1k/trunk/or1200/rtl/verilog/or1200_du.v
617	Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.	lampret	8331d 03h	/or1k/trunk/or1200/rtl/verilog/or1200_du.v
589	No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.	lampret	8340d 20h	/or1k/trunk/or1200/rtl/verilog/or1200_du.v
562	Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.	lampret	8344d 22h	/or1k/trunk/or1200/rtl/verilog/or1200_du.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8355d 20h	/or1k/trunk/or1200/rtl/verilog/or1200_du.v