URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_64x24.v] - Rev 1765

Rev	Log message	Author	Age	Path
1765		root	5628d 22h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_64x24.v
1582	Added support for RAMB16 Xilinx4/Spartan3 primitives	jcastillo	6867d 09h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_64x24.v
1291	Changed behavior of the simulation generic models	lampret	7365d 02h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_64x24.v
1267	Merged branch_qmem into main tree.	lampret	7429d 12h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_64x24.v
1200	mbist signals updated according to newest convention	markom	7600d 12h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_64x24.v
1184	Scan signals mess fixed.	simons	7659d 04h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_64x24.v
1179	BIST interface added for Artisan memory instances.	simons	7667d 07h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_64x24.v
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7793d 19h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_64x24.v
1063	Added BIST scan. Special VS RAMs need to be used to implement BIST.	lampret	7965d 00h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_64x24.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8252d 12h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_64x24.v