URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1ksim/] [testbench/] [cache.c] - Rev 1765

Rev	Log message	Author	Age	Path
1765		root	5741d 17h	/or1k/trunk/or1ksim/testbench/cache.c
631	Real cache access is simulated now.	simons	8338d 18h	/or1k/trunk/or1ksim/testbench/cache.c
621	Cache test works on hardware.	simons	8340d 06h	/or1k/trunk/or1ksim/testbench/cache.c
575	Not needed to be compiled with -O2 optimization any more.	simons	8353d 04h	/or1k/trunk/or1ksim/testbench/cache.c
574	fixed some tests to work	markom	8353d 06h	/or1k/trunk/or1ksim/testbench/cache.c
534	Changed to work with new simulator.	simons	8361d 04h	/or1k/trunk/or1ksim/testbench/cache.c
484	Changed to support execution from various addresses.	simons	8379d 21h	/or1k/trunk/or1ksim/testbench/cache.c
424	memory configuration file joined into .cfg file; *mem.cfg are obsolete; read-only and write-only memory is supported; memory logging is not yet supported; update of testbench - only cache test fails, since it writes to RO memory	markom	8388d 06h	/or1k/trunk/or1ksim/testbench/cache.c
349	Some bugs regarding cache simulation fixed.	simons	8412d 20h	/or1k/trunk/or1ksim/testbench/cache.c
322	IC test repaired.C	simons	8418d 22h	/or1k/trunk/or1ksim/testbench/cache.c
224	added various tests	markom	8436d 04h	/or1k/trunk/or1ksim/testbench/cache.c