URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1ksim/] [testbench/] [except.S] - Rev 600

Rev	Log message	Author	Age	Path
600	No more low/high priority interrupts (PICPR removed). Added tick timer exception.	simons	8339d 06h	/or1k/trunk/or1ksim/testbench/except.S
475	l.jalr r9 is not used any more.	simons	8370d 17h	/or1k/trunk/or1ksim/testbench/except.S
461	DTLBMISS and DPF exceptions are fixed in simulator.	simons	8372d 06h	/or1k/trunk/or1ksim/testbench/except.S
441	Two instructions removed from reset wrapper to save space.	simons	8377d 14h	/or1k/trunk/or1ksim/testbench/except.S
436	Copying from flash to ram only when there is 0xff on address 0.	simons	8377d 15h	/or1k/trunk/or1ksim/testbench/except.S
413	some section changes	markom	8382d 16h	/or1k/trunk/or1ksim/testbench/except.S
410	MMU test added.	simons	8383d 13h	/or1k/trunk/or1ksim/testbench/except.S
409	some minor changes to or1ksim; Testbench except.s modified. Interrupt test almost finished for uart ACV.	markom	8383d 19h	/or1k/trunk/or1ksim/testbench/except.S
371	steps toward joining or32.c and opcode/or32.h of or1ksim and gdb; decode.c moved to or32.c	markom	8393d 19h	/or1k/trunk/or1ksim/testbench/except.S
344	added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model	markom	8405d 18h	/or1k/trunk/or1ksim/testbench/except.S
342	added exception vectors to support and modified section names	markom	8406d 17h	/or1k/trunk/or1ksim/testbench/except.S