URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk] - Rev 342

Rev	Log message	Author	Age	Path
342	added exception vectors to support and modified section names	markom	8280d 09h	/or1k/trunk
341	added VAPI for uart; uart 16550 support, some bugs fixed	markom	8280d 11h	/or1k/trunk
340	Added hpint vector	lampret	8280d 11h	/or1k/trunk
339	Added setpc test	lampret	8280d 11h	/or1k/trunk
338	Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)	lampret	8280d 11h	/or1k/trunk
337	Fixed tick timer interrupt reporting by using TTCR[IP] bit.	lampret	8280d 11h	/or1k/trunk
336	VAPI works	markom	8281d 06h	/or1k/trunk
335	some small bugs fixed	markom	8281d 08h	/or1k/trunk
334	removed vapi client file	markom	8281d 10h	/or1k/trunk
333	small bug fixed	markom	8281d 13h	/or1k/trunk
332	removed fixed irq numbering from pic.h; tick timer section added	markom	8281d 13h	/or1k/trunk
331	dependecy is required by history analisis	markom	8281d 14h	/or1k/trunk
330	Cache test	lampret	8281d 18h	/or1k/trunk
329	Now using macros from spr_defs.h	lampret	8281d 18h	/or1k/trunk
328	Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.	lampret	8281d 19h	/or1k/trunk
327	simulate_dc_mmu_load() was calling insn cache/mmu routines instead of data cache/mmu. Fixed.	lampret	8281d 20h	/or1k/trunk
326	More realistic default cache type.	lampret	8281d 20h	/or1k/trunk
325	minor ethernet testbench modifications	erez	8282d 23h	/or1k/trunk
324	added initial ethernet RX simulation (very simple for now)	erez	8282d 23h	/or1k/trunk
323	small fix	erez	8282d 23h	/or1k/trunk