URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk] - Rev 402

Rev	Log message	Author	Age	Path
402	Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32	lampret	8258d 17h	/or1k/trunk
401	* empty log message *	simons	8262d 03h	/or1k/trunk
400	force_dslot_fetch does not work - allways zero.	simons	8262d 03h	/or1k/trunk
399	Trap insn couses break after exits ex_insn.	simons	8262d 03h	/or1k/trunk
398	added register field defines	ivang	8264d 09h	/or1k/trunk
397	removed or16 architecture	markom	8264d 10h	/or1k/trunk
396	added missing file	markom	8264d 12h	/or1k/trunk
395	removed obsolete dependency and history from cpu section	markom	8264d 14h	/or1k/trunk
394	dependency joined with dependstats; history moved to sim section	markom	8264d 15h	/or1k/trunk
393	messages: exception on many places changed to abort	markom	8264d 15h	/or1k/trunk
391	Fixed except_stop width and fixed EX PC for 1400444f no-ops.	lampret	8264d 23h	/or1k/trunk
390	Changed instantiation name of VS RAMs.	lampret	8265d 01h	/or1k/trunk
389	Changed default delay for load and store in superscalar cpu.	lampret	8265d 01h	/or1k/trunk
388	Added comments for cpu section.	lampret	8265d 01h	/or1k/trunk
387	Now FPGA and ASIC target are separate.	lampret	8265d 03h	/or1k/trunk
386	Fixed VS RAM instantiation - again.	lampret	8265d 03h	/or1k/trunk
385	check testbench now modified to work with new report output	markom	8265d 09h	/or1k/trunk
384	modified simmem.cfg structure! ADD > BEFORE EACH LINE!	markom	8265d 10h	/or1k/trunk
383	modified simmem.cfg structure! ADD	markom	8265d 10h	/or1k/trunk
382	bitmask function bug fixed	markom	8265d 12h	/or1k/trunk