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[/] [pairing/] [trunk/] [rtl] - Rev 32

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32 changed surname: Xing -> Hsing. homer.xing 4597d 01h /pairing/trunk/rtl
31 accurate source code copyright comment header homer.xing 4597d 01h /pairing/trunk/rtl
30 LGPL header homer.xing 4607d 05h /pairing/trunk/rtl
29 default net type is wire homer.xing 4614d 01h /pairing/trunk/rtl
28 Non-net port XXX cannot be of mode input, when using the "`default_nettype none" to turn off automatic inference of wires in the design. ha ha homer.xing 4614d 04h /pairing/trunk/rtl
27 definition for undefined wire homer.xing 4614d 05h /pairing/trunk/rtl
24 LGPL claim in each source hdl file homer.xing 4628d 01h /pairing/trunk/rtl
23 LGPL license text homer.xing 4628d 01h /pairing/trunk/rtl
22 Change TAB to space homer.xing 4628d 03h /pairing/trunk/rtl
17 use logic for $f3m_mux6$ homer.xing 4630d 00h /pairing/trunk/rtl
12 Simplify the interface of the core. homer.xing 4630d 06h /pairing/trunk/rtl
11 Cheers! as fast as a rocket homer.xing 4631d 02h /pairing/trunk/rtl
10 Ho ho, better circuit homer.xing 4631d 20h /pairing/trunk/rtl
9 Add constrains file for ISE homer.xing 4632d 23h /pairing/trunk/rtl
8 Finished Tate Pairing. Ha ha ha homer.xing 4633d 00h /pairing/trunk/rtl
7 Finish inversion @ f33m homer.xing 4641d 05h /pairing/trunk/rtl
6 add testbench for $f33m$. homer.xing 4642d 05h /pairing/trunk/rtl
5 rename director : verilog/ -> rtl/ homer.xing 4642d 05h /pairing/trunk/rtl
3 finish Duursma Lee algorithm. doing f33m module homer.xing 4643d 03h /pairing/trunk/verilog
2 upload code for Duursma-Lee algorithm. I am still developing them. homer.xing 4644d 02h /pairing/trunk/verilog

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