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[/] [pairing/] [trunk] - Rev 33

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33 new email & English name of the author homer.xing 4478d 21h /pairing/trunk
32 changed surname: Xing -> Hsing. homer.xing 4478d 22h /pairing/trunk
31 accurate source code copyright comment header homer.xing 4478d 22h /pairing/trunk
30 LGPL header homer.xing 4489d 02h /pairing/trunk
29 default net type is wire homer.xing 4495d 22h /pairing/trunk
28 Non-net port XXX cannot be of mode input, when using the "`default_nettype none" to turn off automatic inference of wires in the design. ha ha homer.xing 4496d 01h /pairing/trunk
27 definition for undefined wire homer.xing 4496d 01h /pairing/trunk
26 Detailed description for the ModelSim macro file and the main test bench file homer.xing 4501d 21h /pairing/trunk
25 simulation scripts and readme-file explaining how to start the simulation homer.xing 4501d 22h /pairing/trunk
24 LGPL claim in each source hdl file homer.xing 4509d 22h /pairing/trunk
23 LGPL license text homer.xing 4509d 22h /pairing/trunk
22 Change TAB to space homer.xing 4509d 23h /pairing/trunk
21 Add detailed input data capture condition in the document homer.xing 4510d 00h /pairing/trunk
20 Add a module and a testbench for Xilinx ISE post-route simulation homer.xing 4511d 02h /pairing/trunk
19 Update synthesis result homer.xing 4511d 19h /pairing/trunk
18 add synthesis result homer.xing 4511d 19h /pairing/trunk
17 use logic for $f3m_mux6$ homer.xing 4511d 21h /pairing/trunk
16 Add synthesis configuration files homer.xing 4512d 00h /pairing/trunk
15 add document. ha ha ha homer.xing 4512d 01h /pairing/trunk
14 Move constraint file homer.xing 4512d 02h /pairing/trunk

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