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[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog] - Rev 130

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Rev Log message Author Age Path
130 The wbs B3 to B2 translation logic had wrong reset wire connected! mihad 7520d 07h /pci/tags/asyst_2/rtl/verilog
128 Some warning cleanup. simons 7521d 10h /pci/tags/asyst_2/rtl/verilog
126 ifdef - endif statements put in separate lines for flint compatibility. simons 7529d 03h /pci/tags/asyst_2/rtl/verilog
124 Added missing signals to 2 sensitivity lists. Everything works the same as before. tadejm 7567d 10h /pci/tags/asyst_2/rtl/verilog
122 mbist signals updated according to newest convention markom 7574d 10h /pci/tags/asyst_2/rtl/verilog
117 WB Master is now WISHBONE B3 compatible. tadejm 7630d 22h /pci/tags/asyst_2/rtl/verilog
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7630d 22h /pci/tags/asyst_2/rtl/verilog
115 Added signals for WB Master B3. tadejm 7630d 22h /pci/tags/asyst_2/rtl/verilog
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7638d 01h /pci/tags/asyst_2/rtl/verilog
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7638d 06h /pci/tags/asyst_2/rtl/verilog
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.		 mihad 7640d 05h /pci/tags/asyst_2/rtl/verilog
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7644d 03h /pci/tags/asyst_2/rtl/verilog
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7649d 01h /pci/tags/asyst_2/rtl/verilog
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7654d 11h /pci/tags/asyst_2/rtl/verilog
94 Changed one critical PCI bus signal logic. mihad 7701d 09h /pci/tags/asyst_2/rtl/verilog
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7779d 06h /pci/tags/asyst_2/rtl/verilog
86 Entered the option to disable no response counter in wb master. mihad 7791d 04h /pci/tags/asyst_2/rtl/verilog
83 Cleaned up the code. No functional changes. mihad 7820d 01h /pci/tags/asyst_2/rtl/verilog
81 Updated synchronization in top level fifo modules. mihad 7833d 21h /pci/tags/asyst_2/rtl/verilog
79 Updated. mihad 7837d 02h /pci/tags/asyst_2/rtl/verilog

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