URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_3/] [rtl/] [verilog/] [pci_user_constants.v] - Rev 132

Rev	Log message	Author	Age	Path
132	Compact PCI Hot Swap support added. New testcases added. Specification updated. Test application changed to support WB B3 cycles.	mihad	7502d 02h	/pci/tags/asyst_3/rtl/verilog/pci_user_constants.v
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7639d 19h	/pci/tags/asyst_3/rtl/verilog/pci_user_constants.v
86	Entered the option to disable no response counter in wb master.	mihad	7781d 21h	/pci/tags/asyst_3/rtl/verilog/pci_user_constants.v
79	Updated.	mihad	7827d 20h	/pci/tags/asyst_3/rtl/verilog/pci_user_constants.v
78	Old files with wrong names removed.	mihad	7827d 20h	/pci/tags/asyst_3/rtl/verilog/pci_user_constants.v
73	Bug fixes, testcases added.	mihad	7833d 21h	/pci/tags/asyst_3/rtl/verilog/pci_user_constants.v
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7946d 19h	/pci/tags/asyst_3/rtl/verilog/pci_user_constants.v
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7995d 02h	/pci/tags/asyst_3/rtl/verilog/pci_user_constants.v
33	Added some testcases, removed un-needed fifo signals	mihad	8156d 01h	/pci/tags/asyst_3/rtl/verilog/pci_user_constants.v
18	* empty log message *	mihad	8187d 22h	/pci/tags/asyst_3/rtl/verilog/pci_user_constants.v