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[/] [pci/] [tags/] [asyst_3/] [rtl] - Rev 49

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Rev Log message Author Age Path
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7999d 15h /pci/tags/asyst_3/rtl
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 7999d 15h /pci/tags/asyst_3/rtl
47 Known issues repaired mihad 7999d 21h /pci/tags/asyst_3/rtl
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 8004d 16h /pci/tags/asyst_3/rtl
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8005d 21h /pci/tags/asyst_3/rtl
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8151d 01h /pci/tags/asyst_3/rtl
33 Added some testcases, removed un-needed fifo signals mihad 8166d 20h /pci/tags/asyst_3/rtl
32 Added include statement that was missing and causing errors mihad 8174d 17h /pci/tags/asyst_3/rtl
26 Modified testbench and fixed some bugs mihad 8180d 16h /pci/tags/asyst_3/rtl
23 *** empty log message *** mihad 8198d 16h /pci/tags/asyst_3/rtl
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8198d 17h /pci/tags/asyst_3/rtl
19 *** empty log message *** mihad 8198d 17h /pci/tags/asyst_3/rtl
18 *** empty log message *** mihad 8198d 18h /pci/tags/asyst_3/rtl
7 Updated all files with inclusion of timescale file for simulation purposes. mihad 8318d 00h /pci/tags/asyst_3/rtl
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8318d 00h /pci/tags/asyst_3/rtl
2 New project directory structure mihad 8320d 17h /pci/tags/asyst_3/rtl

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