OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_3/] [rtl] - Rev 94

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
94 Changed one critical PCI bus signal logic. mihad 7703d 07h /pci/tags/asyst_3/rtl
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.
mihad 7781d 04h /pci/tags/asyst_3/rtl
86 Entered the option to disable no response counter in wb master. mihad 7793d 02h /pci/tags/asyst_3/rtl
83 Cleaned up the code. No functional changes. mihad 7821d 23h /pci/tags/asyst_3/rtl
81 Updated synchronization in top level fifo modules. mihad 7835d 19h /pci/tags/asyst_3/rtl
79 Updated. mihad 7839d 00h /pci/tags/asyst_3/rtl
78 Old files with wrong names removed. mihad 7839d 01h /pci/tags/asyst_3/rtl
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7839d 01h /pci/tags/asyst_3/rtl
73 Bug fixes, testcases added. mihad 7845d 01h /pci/tags/asyst_3/rtl
72 *** empty log message *** mihad 7892d 05h /pci/tags/asyst_3/rtl
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.
mihad 7899d 21h /pci/tags/asyst_3/rtl
69 Changed BIST signal names etc.. mihad 7937d 04h /pci/tags/asyst_3/rtl
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7940d 14h /pci/tags/asyst_3/rtl
67 Changed BIST signals for RAMs. tadejm 7940d 19h /pci/tags/asyst_3/rtl
66 Changed empty status generation in pciw_fifo_control.v mihad 7944d 05h /pci/tags/asyst_3/rtl
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7947d 03h /pci/tags/asyst_3/rtl
63 Added additional testcase and changed rst name in BIST to trst mihad 7947d 07h /pci/tags/asyst_3/rtl
62 Added BIST signals for RAMs. mihad 7950d 00h /pci/tags/asyst_3/rtl
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7958d 00h /pci/tags/asyst_3/rtl
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7958d 01h /pci/tags/asyst_3/rtl

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.