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[/] [pci/] [tags/] [asyst_3] - Rev 84

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Rev Log message Author Age Path
84 Changed vendor ID. mihad 7794d 18h /pci/tags/asyst_3
83 Cleaned up the code. No functional changes. mihad 7819d 16h /pci/tags/asyst_3
81 Updated synchronization in top level fifo modules. mihad 7833d 13h /pci/tags/asyst_3
79 Updated. mihad 7836d 18h /pci/tags/asyst_3
78 Old files with wrong names removed. mihad 7836d 18h /pci/tags/asyst_3
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7836d 18h /pci/tags/asyst_3
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7839d 18h /pci/tags/asyst_3
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7842d 19h /pci/tags/asyst_3
73 Bug fixes, testcases added. mihad 7842d 19h /pci/tags/asyst_3
72 *** empty log message *** mihad 7889d 23h /pci/tags/asyst_3
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7897d 14h /pci/tags/asyst_3
69 Changed BIST signal names etc.. mihad 7934d 22h /pci/tags/asyst_3
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7938d 07h /pci/tags/asyst_3
67 Changed BIST signals for RAMs. tadejm 7938d 12h /pci/tags/asyst_3
66 Changed empty status generation in pciw_fifo_control.v mihad 7941d 23h /pci/tags/asyst_3
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7944d 21h /pci/tags/asyst_3
64 The testcase I just added in previous revision repaired mihad 7944d 23h /pci/tags/asyst_3
63 Added additional testcase and changed rst name in BIST to trst mihad 7945d 01h /pci/tags/asyst_3
62 Added BIST signals for RAMs. mihad 7947d 18h /pci/tags/asyst_3
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7955d 18h /pci/tags/asyst_3

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