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[/] [pci/] [tags/] [rel_1/] [rtl/] [verilog/] [wbr_fifo_control.v] - Rev 58

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Rev Log message Author Age Path
58 Removed all logic from asynchronous reset network mihad 7981d 22h /pci/tags/rel_1/rtl/verilog/wbr_fifo_control.v
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8217d 23h /pci/tags/rel_1/rtl/verilog/wbr_fifo_control.v
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8337d 06h /pci/tags/rel_1/rtl/verilog/wbr_fifo_control.v
2 New project directory structure mihad 8339d 22h /pci/tags/rel_1/rtl/verilog/wbr_fifo_control.v

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