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[/] [pci/] [tags/] [rel_10/] - Rev 104

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Rev Log message Author Age Path
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7658d 01h /pci/tags/rel_10
103 Added test application and modified files to support it. mihad 7704d 22h /pci/tags/rel_10
102 Cleanup! mihad 7704d 22h /pci/tags/rel_10
101 Added simulation files. mihad 7704d 22h /pci/tags/rel_10
100 Cleanup! mihad 7704d 22h /pci/tags/rel_10
99 Cleanup! mihad 7704d 23h /pci/tags/rel_10
98 Cleanup. mihad 7704d 23h /pci/tags/rel_10
97 Doing a little bit of cleanup. mihad 7704d 23h /pci/tags/rel_10
96 Update! mihad 7704d 23h /pci/tags/rel_10
95 Removed this file, because it was too large - long download time. mihad 7704d 23h /pci/tags/rel_10
94 Changed one critical PCI bus signal logic. mihad 7704d 23h /pci/tags/rel_10
93 Added a test application! mihad 7705d 06h /pci/tags/rel_10
92 Update! mihad 7705d 07h /pci/tags/rel_10
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7740d 20h /pci/tags/rel_10
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7740d 20h /pci/tags/rel_10
89 Burst 2 error fixed. mihad 7776d 21h /pci/tags/rel_10
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7782d 20h /pci/tags/rel_10
87 Updated acording to RTL changes. mihad 7794d 18h /pci/tags/rel_10
86 Entered the option to disable no response counter in wb master. mihad 7794d 18h /pci/tags/rel_10
85 Changed Vendor ID defines. mihad 7794d 22h /pci/tags/rel_10

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