OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_11/] [bench] - Rev 107

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7642d 09h /pci/tags/rel_11/bench
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7647d 07h /pci/tags/rel_11/bench
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7652d 17h /pci/tags/rel_11/bench
92 Update! mihad 7699d 23h /pci/tags/rel_11/bench
89 Burst 2 error fixed. mihad 7771d 13h /pci/tags/rel_11/bench
87 Updated acording to RTL changes. mihad 7789d 10h /pci/tags/rel_11/bench
81 Updated synchronization in top level fifo modules. mihad 7832d 03h /pci/tags/rel_11/bench
73 Bug fixes, testcases added. mihad 7841d 09h /pci/tags/rel_11/bench
69 Changed BIST signal names etc.. mihad 7933d 12h /pci/tags/rel_11/bench
66 Changed empty status generation in pciw_fifo_control.v mihad 7940d 13h /pci/tags/rel_11/bench
64 The testcase I just added in previous revision repaired mihad 7943d 13h /pci/tags/rel_11/bench
63 Added additional testcase and changed rst name in BIST to trst mihad 7943d 15h /pci/tags/rel_11/bench
62 Added BIST signals for RAMs. mihad 7946d 08h /pci/tags/rel_11/bench
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7959d 15h /pci/tags/rel_11/bench
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7993d 08h /pci/tags/rel_11/bench
52 Oops, never before noticed that OC header is missing mihad 7993d 16h /pci/tags/rel_11/bench
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7993d 16h /pci/tags/rel_11/bench
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8002d 14h /pci/tags/rel_11/bench
44 Added for testing of Configuration Cycles Type 1 mihad 8002d 15h /pci/tags/rel_11/bench
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 8002d 15h /pci/tags/rel_11/bench

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.