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[/] [pci/] [tags/] [rel_11/] [bench] - Rev 66

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Rev Log message Author Age Path
66 Changed empty status generation in pciw_fifo_control.v mihad 7940d 11h /pci/tags/rel_11/bench
64 The testcase I just added in previous revision repaired mihad 7943d 11h /pci/tags/rel_11/bench
63 Added additional testcase and changed rst name in BIST to trst mihad 7943d 13h /pci/tags/rel_11/bench
62 Added BIST signals for RAMs. mihad 7946d 06h /pci/tags/rel_11/bench
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7959d 13h /pci/tags/rel_11/bench
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7993d 06h /pci/tags/rel_11/bench
52 Oops, never before noticed that OC header is missing mihad 7993d 14h /pci/tags/rel_11/bench
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7993d 14h /pci/tags/rel_11/bench
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8002d 12h /pci/tags/rel_11/bench
44 Added for testing of Configuration Cycles Type 1 mihad 8002d 13h /pci/tags/rel_11/bench
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 8002d 13h /pci/tags/rel_11/bench
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8147d 16h /pci/tags/rel_11/bench
34 Added missing include statements mihad 8162d 14h /pci/tags/rel_11/bench
33 Added some testcases, removed un-needed fifo signals mihad 8163d 11h /pci/tags/rel_11/bench
26 Modified testbench and fixed some bugs mihad 8177d 07h /pci/tags/rel_11/bench
19 *** empty log message *** mihad 8195d 08h /pci/tags/rel_11/bench
15 Initial testbench import. Still under development mihad 8195d 10h /pci/tags/rel_11/bench
3 New project directory structure mihad 8317d 07h /pci/tags/rel_11/bench

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