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[/] [pci/] [tags/] [rel_11] - Rev 96

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Rev Log message Author Age Path
96 Update! mihad 7698d 19h /pci/tags/rel_11
95 Removed this file, because it was too large - long download time. mihad 7698d 19h /pci/tags/rel_11
94 Changed one critical PCI bus signal logic. mihad 7698d 19h /pci/tags/rel_11
93 Added a test application! mihad 7699d 02h /pci/tags/rel_11
92 Update! mihad 7699d 02h /pci/tags/rel_11
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7734d 16h /pci/tags/rel_11
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7734d 16h /pci/tags/rel_11
89 Burst 2 error fixed. mihad 7770d 17h /pci/tags/rel_11
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7776d 16h /pci/tags/rel_11
87 Updated acording to RTL changes. mihad 7788d 13h /pci/tags/rel_11
86 Entered the option to disable no response counter in wb master. mihad 7788d 13h /pci/tags/rel_11
85 Changed Vendor ID defines. mihad 7788d 17h /pci/tags/rel_11
84 Changed vendor ID. mihad 7792d 12h /pci/tags/rel_11
83 Cleaned up the code. No functional changes. mihad 7817d 10h /pci/tags/rel_11
81 Updated synchronization in top level fifo modules. mihad 7831d 07h /pci/tags/rel_11
79 Updated. mihad 7834d 12h /pci/tags/rel_11
78 Old files with wrong names removed. mihad 7834d 12h /pci/tags/rel_11
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7834d 12h /pci/tags/rel_11
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7837d 12h /pci/tags/rel_11
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7840d 12h /pci/tags/rel_11

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