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[/] [pci/] [tags/] [rel_12/] [rtl] - Rev 154

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Rev	Log message	Author	Age	Path
154	New directory structure.	root	5607d 03h	/pci/tags/rel_12/rtl
129	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7525d 02h	/pci/tags/rel_12/rtl
128	Some warning cleanup.	simons	7525d 02h	/pci/tags/rel_12/rtl
126	ifdef - endif statements put in separate lines for flint compatibility.	simons	7532d 19h	/pci/tags/rel_12/rtl
124	Added missing signals to 2 sensitivity lists. Everything works the same as before.	tadejm	7571d 02h	/pci/tags/rel_12/rtl
122	mbist signals updated according to newest convention	markom	7578d 02h	/pci/tags/rel_12/rtl
117	WB Master is now WISHBONE B3 compatible.	tadejm	7634d 14h	/pci/tags/rel_12/rtl
116	Corrected bug when writing to FIFO (now it is registered).	tadejm	7634d 14h	/pci/tags/rel_12/rtl
115	Added signals for WB Master B3.	tadejm	7634d 14h	/pci/tags/rel_12/rtl
113	ifdefs moved to thier own lines, this confuses some of the tools.	simons	7641d 17h	/pci/tags/rel_12/rtl
111	synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.	simons	7641d 22h	/pci/tags/rel_12/rtl
110	Module that converts slave WISHBONE B3 accesses to WISHBONE B2 accesses with CAB.	mihad	7643d 21h	/pci/tags/rel_12/rtl
108	Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.	tadejm	7647d 19h	/pci/tags/rel_12/rtl
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7652d 17h	/pci/tags/rel_12/rtl
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7658d 03h	/pci/tags/rel_12/rtl
94	Changed one critical PCI bus signal logic.	mihad	7705d 01h	/pci/tags/rel_12/rtl
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7782d 22h	/pci/tags/rel_12/rtl
86	Entered the option to disable no response counter in wb master.	mihad	7794d 20h	/pci/tags/rel_12/rtl
83	Cleaned up the code. No functional changes.	mihad	7823d 17h	/pci/tags/rel_12/rtl
81	Updated synchronization in top level fifo modules.	mihad	7837d 13h	/pci/tags/rel_12/rtl

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Subversion Repositories pci

[/] [pci/] [tags/] [rel_12/] [rtl] - Rev 154

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