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[/] [pci/] [tags/] [rel_12/] [rtl] - Rev 55

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Rev Log message Author Age Path
55 Changed state machine encoding to true one-hot mihad 7965d 20h /pci/tags/rel_12/rtl
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7999d 01h /pci/tags/rel_12/rtl
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7999d 05h /pci/tags/rel_12/rtl
50 Got rid of undef directives mihad 8001d 21h /pci/tags/rel_12/rtl
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8001d 21h /pci/tags/rel_12/rtl
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 8001d 21h /pci/tags/rel_12/rtl
47 Known issues repaired mihad 8002d 03h /pci/tags/rel_12/rtl
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 8006d 21h /pci/tags/rel_12/rtl
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8008d 03h /pci/tags/rel_12/rtl
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8153d 07h /pci/tags/rel_12/rtl
33 Added some testcases, removed un-needed fifo signals mihad 8169d 02h /pci/tags/rel_12/rtl
32 Added include statement that was missing and causing errors mihad 8176d 23h /pci/tags/rel_12/rtl
26 Modified testbench and fixed some bugs mihad 8182d 22h /pci/tags/rel_12/rtl
23 *** empty log message *** mihad 8200d 22h /pci/tags/rel_12/rtl
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8200d 23h /pci/tags/rel_12/rtl
19 *** empty log message *** mihad 8200d 23h /pci/tags/rel_12/rtl
18 *** empty log message *** mihad 8200d 23h /pci/tags/rel_12/rtl
7 Updated all files with inclusion of timescale file for simulation purposes. mihad 8320d 06h /pci/tags/rel_12/rtl
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8320d 06h /pci/tags/rel_12/rtl
2 New project directory structure mihad 8322d 23h /pci/tags/rel_12/rtl

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