URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_12/] [sim/] [rtl_sim/] [run/] [run_pci_sim_regr.scr] - Rev 104

Rev	Log message	Author	Age	Path
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7658d 16h	/pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
92	Update!	mihad	7705d 22h	/pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
81	Updated synchronization in top level fifo modules.	mihad	7838d 03h	/pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
73	Bug fixes, testcases added.	mihad	7847d 09h	/pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
63	Added additional testcase and changed rst name in BIST to trst	mihad	7949d 15h	/pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7960d 07h	/pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8008d 14h	/pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
26	Modified testbench and fixed some bugs	mihad	8183d 08h	/pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
17	* empty log message *	mihad	8201d 11h	/pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr