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[/] [pci/] [tags/] [rel_12/] [sim/] [rtl_sim/] [run/] [run_pci_sim_regr.scr] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5589d 12h /pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
129 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7507d 11h /pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
118 Some minor changes due to changes in core. tadejm 7616d 23h /pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7635d 02h /pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7640d 12h /pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
92 Update! mihad 7687d 18h /pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
81 Updated synchronization in top level fifo modules. mihad 7819d 22h /pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
73 Bug fixes, testcases added. mihad 7829d 04h /pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
63 Added additional testcase and changed rst name in BIST to trst mihad 7931d 10h /pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7942d 03h /pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7990d 09h /pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
26 Modified testbench and fixed some bugs mihad 8165d 04h /pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
17 *** empty log message *** mihad 8183d 06h /pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr

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