URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_12/] [sim/] [rtl_sim/] [run/] [run_pci_sim_regr.scr] - Rev 81

Rev	Log message	Author	Age	Path
81	Updated synchronization in top level fifo modules.	mihad	7867d 22h	/pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
73	Bug fixes, testcases added.	mihad	7877d 04h	/pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
63	Added additional testcase and changed rst name in BIST to trst	mihad	7979d 10h	/pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7990d 02h	/pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8038d 09h	/pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
26	Modified testbench and fixed some bugs	mihad	8213d 03h	/pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr
17	* empty log message *	mihad	8231d 06h	/pci/tags/rel_12/sim/rtl_sim/run/run_pci_sim_regr.scr