URL https://opencores.org/ocsvn/pci/pci/trunk

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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [delayed_sync.v] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5581d 08h	/pci/tags/rel_3/rtl/verilog/delayed_sync.v
74	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7821d 00h	/pci/tags/rel_3/rtl/verilog/delayed_sync.v
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7939d 06h	/pci/tags/rel_3/rtl/verilog/delayed_sync.v
33	Added some testcases, removed un-needed fifo signals	mihad	8143d 04h	/pci/tags/rel_3/rtl/verilog/delayed_sync.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8175d 01h	/pci/tags/rel_3/rtl/verilog/delayed_sync.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8294d 08h	/pci/tags/rel_3/rtl/verilog/delayed_sync.v
2	New project directory structure	mihad	8297d 00h	/pci/tags/rel_3/rtl/verilog/delayed_sync.v