URL https://opencores.org/ocsvn/pci/pci/trunk

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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [out_reg.v] - Rev 74

Rev	Log message	Author	Age	Path
74	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7822d 17h	/pci/tags/rel_3/rtl/verilog/out_reg.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8176d 18h	/pci/tags/rel_3/rtl/verilog/out_reg.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8296d 01h	/pci/tags/rel_3/rtl/verilog/out_reg.v
2	New project directory structure	mihad	8298d 17h	/pci/tags/rel_3/rtl/verilog/out_reg.v