URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pci_target32_sm.v] - Rev 55

Rev	Log message	Author	Age	Path
55	Changed state machine encoding to true one-hot	mihad	7941d 09h	/pci/tags/rel_3/rtl/verilog/pci_target32_sm.v
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7974d 18h	/pci/tags/rel_3/rtl/verilog/pci_target32_sm.v
26	Modified testbench and fixed some bugs	mihad	8158d 11h	/pci/tags/rel_3/rtl/verilog/pci_target32_sm.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8176d 12h	/pci/tags/rel_3/rtl/verilog/pci_target32_sm.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8295d 19h	/pci/tags/rel_3/rtl/verilog/pci_target32_sm.v
2	New project directory structure	mihad	8298d 12h	/pci/tags/rel_3/rtl/verilog/pci_target32_sm.v