URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pci_target_unit.v] - Rev 63

Rev	Log message	Author	Age	Path
63	Added additional testcase and changed rst name in BIST to trst	mihad	7926d 06h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
62	Added BIST signals for RAMs.	mihad	7928d 23h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
58	Removed all logic from asynchronous reset network	mihad	7942d 01h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
33	Added some testcases, removed un-needed fifo signals	mihad	8146d 05h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
26	Modified testbench and fixed some bugs	mihad	8160d 00h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8178d 01h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8297d 08h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
2	New project directory structure	mihad	8300d 01h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v