URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pci_target_unit.v] - Rev 68

Rev	Log message	Author	Age	Path
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7919d 11h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
67	Changed BIST signals for RAMs.	tadejm	7919d 16h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
63	Added additional testcase and changed rst name in BIST to trst	mihad	7926d 05h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
62	Added BIST signals for RAMs.	mihad	7928d 22h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
58	Removed all logic from asynchronous reset network	mihad	7941d 23h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
33	Added some testcases, removed un-needed fifo signals	mihad	8146d 03h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
26	Modified testbench and fixed some bugs	mihad	8159d 22h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8177d 23h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8297d 07h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
2	New project directory structure	mihad	8299d 23h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v